A Clock-Gating Method for Low-Power LSI Design
نویسندگان
چکیده
This paper describes an automated layout design technique for the gated-clock design. Two issues must be considered for gated-clock circuits to work correctly. One is to minimize the skew for gated-clock nets. The other is to keep timing constraints for enable-logic parts. We propose the layout design technique to taking these things into consideration. We developed GatedClock Tree Synthesizer for the first issue, and Timing Constraints Generator and Clock Delay Estimator for the second. We applied it to a practical gated-clock circuit. By our technique, the clock-skew could be less than 0.2ns keeping timing constraints for enable-logic parts.
منابع مشابه
Analysis and Design of Low Power Flip-Flop Based on Sleepy Stack Approach
Low power is an important principal theme in today’s electronics industry. So this Low Power Pulse Triggered Flip Flop reviews various methodologies for designing low power circuits and systems. It describes the many issues facing designers at architectural, logic, circuit and device levels and presents some of the techniques that have been proposed to overcome these difficulties. This paper co...
متن کاملLow Power Approach of Clock Gating in Synchronous System like FIFO: A Novel Clock Gating Approach and Comparative Analysis
A new technique of clock gating is presented to reduce dynamic power consumption. This new clock gating technique is applied on a synchronous design. Here the synchronous design is FIFO (First -in -Firstout). With the help of clock gating method unwanted switching activities can be reduced. Mainly Tri-state Buffer is used to design this new low power approach. The RTL schematic of FIFO without ...
متن کاملLow Power Baseband Modem LSI
Mitsubishi Electric Corporation has developed a low power baseband modem LSI for W-CDMA mobile phones. The LSI was installed in D900i, achieving approx. 170/90 minutes of continuous talk time for voice/video phones, and approx. 550/420 hours of continuous standby time in stationary/moving states respectively. The architecture of this LSI is similar to that of the baseband modem LSI chipset used...
متن کاملDesign and Implementation of Field Programmable Gate Array Based Baseband Processor for Passive Radio Frequency Identification Tag (TECHNICAL NOTE)
In this paper, an Ultra High Frequency (UHF) base band processor for a passive tag is presented. It proposes a Radio Frequency Identification (RFID) tag digital base band architecture which is compatible with the EPC C C2/ISO18000-6B protocol. Several design approaches such as clock gating technique, clock strobe design and clock management are used. In order to reduce the area Decimal Matrix C...
متن کاملClock Gating for Dynamic Power Reduction in Synchronous Circuits
In this paper clock gating technique is presented for low power VLSI (very large scale integration) circuit design. Clock in digital circuits is used for synchronization of various components. Clock power is a major source of dynamic power consumed in synchronous circuits. Clock-gating is a well-known technique to reduce clock power. In clock gating clock to an idle block is disabled. Thus sign...
متن کامل